SoC-e – Ethernet communication solutions based on FPGA technology. SoC-e is pioneer in developing a portfolio of IP cores that implement the leading-edge networking and synchronization technologies for critical systems.
SoC-e FPGAa IP Products catalog (616 downloads)
SoC-e has invested a large effort on R&D activity to develop optimized hardware and software architectures to face the challenges that have arisen when implementing these standards. In the same way, SoC-e takes part in most of the interoperability events contributing to the testing and spreading of these new technologies. In order to allow this intensive R&D activity and in internationalization, this company has reinvested all the profits since its creation and it has enforced its strategy with the integration of SoC-e in Etxe-Tar Corporation, an industrial group reference in innovation.
HSR-PRP Switch IP Core
All hardware low-latency switch for FPGAs
HSR-PRP Switch (HPS) is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP version 3, IEC 62439-3-Clause 5 and 4 respectively) standards for Reliable Ethernet communications. HSR-PRP Switch is a full hardware solution that can be implemented on a low-cost FPGA.
It is a flexible solution for the Energy Market Equipment that will be connected to HSR rings, PRP Lans or will work as Network bridges in the context of IEC 61850.
HSR/PRP Switch IP Core Brochure
HSR-PRP Switch IP core key features:
HSR-PRP Switch IP core customizable features for optimum resources/functionalities trade off:
SoC-e’s Managed Ethernet Switch (MES) IP core is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a Store & Forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Consequently, MES is the perfect switch to implement Ethernet based Industrial Networks.
MES is a tri-speed (10/100/1000 Mpbs) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network.
Furthermore, MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.
MES can be used in combination with SoC-e HSR-PRP Switch IP to introduce HSR and PRP capabilities in the ports that are required. HSR switching approach is Cut Through. Thus, the combination offers the maximum performance and maximum compatibility with the standards.
MES can be supported on Xilinx Spartan-6 and every 7-Series devices.
Managed Ethernet Switch Brochure
MES IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.
Managed Ethernet Switch IP Core key features:
- Managed Ethernet Switch IP Core block diagram -
Supported boards for the Reference Designs:
Full-crossbar IEEE 1588 Ethernet Switch in a single FPGA
SoC-e’s Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices. It does not require external confi guration. It has been designed to address the maximum throughput using the minimum resources.
The switch implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The switch buff ers and verifi es each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, UESsupports IEEE 1588 V2 Transparent Clock functionalities. This feature, that corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.
UES is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks.
UnmanagedEthernetSwitch IP Core Brochure
UES can be combined with our HSR-PRP Switch IP to introduce HSR and PRP capabilities in the required ports. HSR switching approach is Cut-Through. Thus the combination offers the maximum performance and maximum compatibility with the standards.
Unmanaged Ethernet Switch IP core key features:
- UnmanagedEthernet Switch IP Core block diagram -
Supported boards for the Reference Designs:
The SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs. It co-works with a PROFINET software stack running on an external or an internal CPU (Microblaze or ARM9). This IP is an ideal solution for implementing flexible Profinet Automation equipments. The reference design implements PROFINET RT CC-B Line Structure integrating PORT.DE Profinet Software Stack.
Profinet Switch IP Core key functionalities are:
Port A and Port B: they are connected to a Profinet bus. They connect the equipment to a Line topology network.
Port C: it offers a conventional Ethernet link to any on-board or external CPU in order to receive Profinet frames.
- Profinet Switch IP Basic Structure -
The PROFINET Switch IP Core presents MII interface (10/100 Mbps) towards Interlink Port and towards External Ports connected to Ethernet PHYs. These ports have full-duplex interfaces.
The PROFINET Switch IP Core also presents MDIO interface in order to allow host CPU to access the registers of PROFINET Switch and to poll the status of the connected PHY devices.
The Profinet Switch IP Core includes the following functionalities:
TSN stands for Time Sensitive Networking. It is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized, low latency, streaming services through IEEE 802 networks.
TSN is unique in that its streams are delivered with guaranteed bandwidth and deterministic latency. There are many features involved in the multiple standards currently under development. Some of the most relevant features and associated standards are:
TSN is evolving and it is targeting different sectors, like Automotive, Industry, Broadcasting and Aerospace. Therefore, it is expected switching implementations that combine a subset of the available standards and features. This flexibility can be achieved through reconfigurable logic (FPGAs), HDL IPs and embedded software. Thus, programmable SoCs are perfect candidates for TSN implementations.
Time Sensitive Networking (TSN) Switch IP is a non-blocking switching matrix specifically designed to implement Ethernet TSN in Industrial and Aerospace equipment. It can be used as a base for a custom TSN configuration and it can be adapted to support a different subset of the standards.
TSN Switch IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.
TSN Switch IP Core key features:
Supported boards for the Reference Designs:
IEEE 1588-2008, also known PTPv2, offers high accuracy clock synchronization for interconnected systems. There are many sectors that benefit from this protocol, like finance, aerospace and industry. A representative IEEE 1588-2008 case-of-use is the adoption of this protocol as synchronization mechanism in the standard for Substation Automation (IEC 61850).
The following diagram shows a typical application of PTPv2 in Substation Automation System (SAS) application:
In this scenario, the Merging Units sample current and voltage values and timestamp them using IEEE 1588 synchronized timers. The protection relays, IEDs, process these values and reconstruct the status of the grid using these digital values. The IEDs attending this information can apply any control action.
An IEEE 1588 infrastructure requires Master Clock equipment to provide clocking reference, Slave Clocks synchronize with the Master Clocks and Boundary Clocks to communicate different clock domains. Additionally, all networking equipment should be time-aware devices in order to maintain the same level of accuracy in the whole network. In the context of IEEE 1588, the requested featured is named Transparent Clock.
SoC-e provides technology to integrate these functionalities in a very diverse range of equipment:
PreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for Xilinx FPGAs. It is capable of accurately time stamp IEEE 1588 telegrams and also to provide a compatible timer. All these processes are carried out by hardware modules.
PreciseTimeBasic IP comprises different hardware and software elements:
Both versions of TSU can use an internal adjustable timer or take its timer value from another TSU. Thus multiple Ethernet connections can share the same timer or different Ethernet connections may have their individual timer.
PreciseTimeBasic IP Core key features:
Hardware features:
Software features:
The final accuracy obtained in a IEEE 1588 systems depends on many factors (frequency and quality of the local clock, location of the time stamp in the data chain, etc.). As a reference, next figure shows the measured error between the PPS generated by a Commercial Grandmaster equipment and the PPS generated by a Zedboard Avnet Devopment Platfrom which runs LinuxPTP software stack in the ARM processor and uses the PreciseTimeBasic for hardware assisted timestamping (+/- 30 ns).
1588Tiny is a IEEE1588-2008 V2 Slave Only hard-only compliant clock synchronization IP core for Xilinx FPGAs. It is focused on equipments that requires basic IEEE 1588 functionality using the minimum resources. 1588Tiny is capable of accurately time-stamping IEEE 1588 telegrams and also provides a synchronized clock using only hardware modules.
An embedded processor is not required, nor a generic Ethernet MAC. 1588Tiny includes an optimized Ethernet MAC to process PTP frames. It supports Power Profile and IEC 61850 and it can also support other profiles. The reference design targets AVNET Spartan-6 FPGA LX9 Microboard.
1588Tiny key features:
The term IRIG signals is used to refer to a whole group of serial timecodes, which use a continuous stream of binary data to transmit information on date and time. The individual time code formats can be distinguished by the signal characteristics, e.g. modulated versus unmodulated, which require different ways of signal transmission, by the data rate, and by the kind of information included in the transmitted data.
Back in 1956 the TeleCommunication Working Group (TCWG) of the American Inter Range Instrumentation Group (IRIG) was mandated to standardize different time code formats, resulting inIRIG Document 104-60. The latest revision is IRIG Standard 200-04 which is the current version specifying some new codes which also transmit a year number. IRIGB is widely used to synchronize systems in Substation Automation Systems (SAS) and in Defence and Aerospace. Nowadays, it is quite frequent combining IEEE 1588 systems with IRGIB systems. The following diagram maps as an example the functionalities of SoC-e timing related IPs of SAS equipment related to synchronization.
