What is JTAG testing?

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What is JTAG Testing — A Corelis Tutorial

JTAG testing — also called boundary-scan — has grown rapidly since IEEE published it as a standard in 1990. Engineers building reliable electronics now choose JTAG testing first. Its low cost and IC-level access have pushed JTAG well beyond board test into design and field service.

Introduction to JTAG Testing

IEEE Std. 1149.1 defines JTAG. It started as a way to test interconnects on printed circuit boards (PCBs) directly from the integrated circuit (IC). PCBs grew more complex every year. That trend exposed the limits of in-circuit testers (ICTs) and bed-of-nails fixtures.

What is JTAG?

Figure 1. BGA faults are difficult to detect and diagnose without JTAG.

New packaging formats made the problem worse. Ball Grid Array (BGA, shown in Figure 1) and other fine-pitch components shrank component footprints. They also eliminated physical access to most signals.

Bed-of-nails fixtures became much more expensive to design and build. Test coverage suffered at the same time. JTAG/boundary-scan solved both problems in one move: build the test logic directly into the IC.

Today, engineers use JTAG for everything from interconnect testing to flash programming of deployed systems. JTAG keeps evolving. New extensions now target 3D ICs and complex hierarchical systems.

History of JTAG Testing

The Original Standard (1990)

The Joint Test Action Group formed in the 1980s. The group set out to standardize boundary-scan testing. IEEE published the result in 1990 as IEEE Std. 1149.1-1990.

A 1993 revision — 1149.1a — clarified and corrected the original spec. The 1994 supplement 1149.1b added Boundary-Scan Description Language (BSDL). BSDL enabled fast automated test development. Major electronics producers worldwide quickly adopted it. IEEE rolled the lessons learned into the 2001 update.

Extensions for New Applications

New use cases demanded new standards. IEEE-1149.5 (1995) and IEEE-1149.4 (1999) saw low adoption. IEEE-1149.6 (2003) had a slow start. But it now ships in many ICs because its target — high-speed AC-coupled signals — went mainstream. IEEE-1149.7 (2009) addressed low-pin-count systems and ships today in many popular microcontrollers.

Standards for Specific Capabilities

IEEE-1532 (2002) covers in-system configuration of programmable devices. FPGAs and their tooling now treat it as standard. IEEE-1581 (2011) added a convenient way to test high-speed memory interconnects with slow-speed test vectors. Some DDR4 components implement a version of it. IEEE-1149.8.1 (2012) tackles combined capacitive sensing and boundary-scan test.

Modern Embedded Instrumentation

Recent efforts standardize JTAG access to instruments embedded inside ICs. IEEE updated 1149.1 again in 2013. The alternative IEEE-1687 standard followed in 2014. Industry groups now push JTAG into 3D-IC, system-level, and high-speed test. The extensibility of JTAG keeps proving itself.

Further reading: Download the Boundary-Scan for PCB Interconnect Testing whitepaper — or please keep reading.

How Does JTAG Testing Work?

The Boundary-Scan Architecture

JTAG started as a way to test IC interconnects on a PCB without physical probes. Boundary-scan cells — built from multiplexer and latch circuits — sit on every pin. These cells capture data from pin or core-logic signals. They also force data onto pins.

Captured data flows out serially through the JTAG Test Access Port (TAP). The tester compares each value against the expected result. Test data flows back into the cells the same way. A serial data path — the scan path or scan chain — controls all of it.

Why JTAG Beats Traditional Testing

Each pin is individually controllable. That alone eliminates thousands of test vectors normally needed to initialize sequential logic. JTAG drops the count to tens or hundreds. Engineers gain shorter test times, higher coverage, better diagnostics, and lower equipment cost.

Interconnect Test in Practice

Figure 3. Basic principles of an interconnect test.

Figure 3 shows two boundary-scan devices wired through four nets. The first device drives the four inputs of the second with predefined values. Assume two faults: a short between Net2 and Net3, plus an open on Net4. A short behaves as a wired-AND. An open behaves as stuck-at-1.

The tester shifts the patterns into the first boundary-scan register. The second device captures the inputs. The tester shifts those captured values back out and compares them. The results on Net2, Net3, and Net4 — marked in red — fail to match. The tester tags those nets as faulty. Smart algorithms then generate the minimal vector set to isolate every defect.

Beyond Interconnect Testing

Interconnect test is only one use of JTAG. Engineers extended the TAP for in-system programming (ISP), in-circuit emulation (ICE), and embedded functional test. Device vendors add their own instructions and registers. A microprocessor exposes data download, program execution, and register peek-and-poke through the TAP. FPGAs and CPLDs use IEEE-1532 over JTAG for erase, configure, read-back, and control. Embedded IC instruments — voltage probes, current probes, on-chip high-speed test engines — now ride the same TAP.

Watch JTAG Testing in Action

The demonstration below shows JTAG/boundary-scan testing on a real PCB. It illustrates how the Test Access Port shifts patterns through the scan chain. Corelis tools then detect short and open faults automatically.

JTAG Testing Across the Product Life Cycle

JTAG started as a production-phase test method. New extensions to IEEE-1149.1 changed that. Boundary-scan now applies to design, prototype debug, and field service — as Figure 4 shows.

The same test suite validates design testability, drives board bring-up, runs high-volume manufacturing test, and supports field repairs and reprogramming. One investment serves the entire product lifetime.

Figure 4. JTAG tools serve every phase of the product life cycle.

Resources

  • JTAG Tutorial
  • What is JTAG?
  • What is JTAG Whitepaper
  • JTAG Test Overview
  • Technical Guide to JTAG
  • JTAG Test Applications
  • Design for Testability (DFT) Guidelines

References

The IEEE Std 1149.1-1990 — Test Access Port and JTAG Architecture and the Std 1149.1-1994b Supplement are available from IEEE Inc., 345 East 47th Street, New York, NY 10017, USA — 1-800-678-IEEE (USA) / 1-908-981-9667 (outside USA). You can also obtain a copy from https://www.ieee.org/. Contact the Sightsys team for Corelis JTAG hardware and software pricing, demos, or technical consultation in Israel.